In tandem with reduction in size and weight of an electronic device, various electronic components such as a semiconductor chip provided in the electronic device are miniaturized. In addition, a space for packaging the electronic component is extremely limited due to the miniaturization. In addition, in order to further miniaturize and increase the number of functions in the future, it is necessary to increase a package density of a semiconductor chip. Under such circumstances, a three-dimensional packaging technique has been devised.
According to the three-dimensional packaging technique, a plurality of semiconductor chips are laminated and the semiconductor chips are wired to realize high-density packaging of the semiconductor.
In the three-dimensional packaging technique, the semiconductor chip or a Si interposer to connect the semiconductor chip to a substrate has a following electrode structure. That is, the semiconductor chip or the Si interposer has a connecting terminal and an electrode pad section for external connection, on its front and back surfaces. The semiconductor chip or the Si interposer has a conductive member in its inside and a through hole penetrating through the front and back surfaces of the semiconductor chip. The connecting terminal and the electrode pad section are electrically connected through the conductive member formed in the through hole.
Thus, the semiconductor chips, the Si interposers, or the semiconductor chip and the Si interposer each having the above electrode structure are laminated. Thus, the connecting terminal or the electrode pad section formed on the back surface of the semiconductor chip is connected to the connecting terminal or the electrode pad section formed on the front surface of another semiconductor chip. Through this connection, the semiconductor chips or the substrates are wired.
The semiconductor chip or the Si interposer used in the three-dimensional packaging technique is produced through many steps. For example, a conventional method for forming the connecting terminal or the electrode pad for the external connection, and the through hole is implemented by following steps as shown in Patent Literature 1. First, the through hole is filled with a conductive member, and the whole surface of the semiconductor chip or the Si interposer is covered with a resist pattern. Then, the conductive member except for a part on which the connecting terminal or the electrode pad is to be formed is removed by wet-etching, and the connecting terminal or the electrode pad is formed.
FIG. 5 is a flowchart of steps of manufacturing a semiconductor device according to Patent Document 1. FIGS. 6A to 6F are each a cross-sectional view showing a state of the semiconductor device in each step in a manufacturing method of the semiconductor device according to Patent Document 1.
FIG. 6A shows a cross-sectional state of the semiconductor device after five steps have been performed. The five steps include, as shown in FIG. 5, a step of forming a hole in a substrate in a step (S501), a step of forming an insulating film in the hole and on a surface of the substrate in a step (S502), a step of removing the insulating film from the surface of the substrate and a bottom surface of the hole in a step (S503), a step of forming a base conductive member in the hole and on the surface of the substrate in a step (S504), and after the steps are completed, a step of forming a resist on a surface of the base conductive member in a step (S505).
Referring to FIG. 6A, an insulating film 501 is formed on a wall surface of a hole 503 formed in a substrate 502. A base conductive member 504 is formed so as to cover an inside of the hole 503, and an upper part of the substrate 502. A resist 505 is applied and patterned to be formed on a surface of the base conductive member 504.
FIG. 6B shows a cross-sectional state of the semiconductor device after a conductive layer 506 has been formed on the surface of the base conductive member 504 in a step (S506) in FIG. 5. The conductive layer 506 to become the connecting terminal and the electrode pad section is formed on the base conductive member 504 as the basis.
FIG. 6C shows a cross-sectional state of the semiconductor device after the resist 505 has been removed from the surface of the base conductive member 504 in a step (S507) in FIG. 5. The resist 505 is removed and a groove 507 is formed, whereby the conductive layer 506 is divided into a conductive layer 506A to become the connecting terminal or the electrode pad section, and a conductive layer 508 serving as the rest except for the conductive layer 506A.
FIG. 6D shows a cross-sectional state of the semiconductor device after a resist 509 to cover the conductive layer 506A to become the connecting terminal or the electrode pad section has been formed in a step (S508) in FIG. 5.
FIG. 6E shows a cross-sectional state of the semiconductor device after the conductive layer 508 has been removed except for the conductive layer 506A to become the connecting terminal or the electrode pad section in a step (S509) in FIG. 5. The conductive layer 508 is removed by wet-etching except for the conductive layer 506A to become the connecting terminal or the electrode pad section. During the removal, since the conductive layer 506A to become the connecting terminal or the electrode pad section is covered with the resist 509, the conductive layer 506A is protected and can be prevented from being eroded by a wet-etching solution.
FIG. 6F shows a cross-sectional state of the semiconductor device after the base conductive member 504 has been removed except for the conductive layer 506A to become the connecting terminal or the electrode pad section in a step (S510) in FIG. 5, and the resist covering the part to become the connecting terminal or the electrode pad section has been removed in a step (S511). The base conductive member 504 is removed except for the conductive layer 506A to become the connecting terminal or the electrode pad section in the step (S510) in FIG. 5, and the resist 509 covering the conductive layer 506A to become the connecting terminal or the electrode pad section is removed, whereby the conductive layer 506A of the connecting terminal or the electrode pad is formed.
Then, through a step of forming a mask metal on the electrode pad section in a step (S512) in FIG. 5, a step of forming a protective film on a surface except for the electrode pad section in a step (S513), and a step of forming a solder bump on the electrode pad section in a step (S513), the solder bump is formed on the electrode pad section (not shown).
However, as described with reference to FIG. 6E, there is an issue in the conventional method to prevent erosion due to the wet-etching solution used in the post-step by covering the connecting terminal or the electrode pad section with the resist. That is, the issue in the conventional method is that it is necessary to add a photolithography step to cover only the connecting terminal and the electrode pad section with the resist. Thus, the resist material is needed and the step is increased, which causes production cost to increase.
In addition, the resist could flow into a narrow gap between the connecting terminal or the electrode pad section and a part other than the connecting terminal or the electrode pad section. This resist is very hard to remove later, so that the resist residue could cause quality to decline.
In addition, as shown in FIG. 6B, in the case where a thickness of the conductive layer 506 is small, a recessed shape is generated in a center of the hole 503. When the conductive layer 506 having the recessed shape is covered with the resist to prevent erosion due to the wet-etching solution used in the post-step, the resist could flow into an inner part of the conductive layer having the recessed shape. This resist is hard to remove later, so that the resist residue could cause quality to decline.